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w9864g6jb 1 m ? ? publication release date: jun. 25 , 2010 - 1 - revision a 0 1 table of contents - 1. general description ................................ ................................ ................................ .............. 3 2. features ................................ ................................ ................................ ................................ ...... 3 3. order information ................................ ................................ ................................ .................. 4 4. ball configuration ................................ ................................ ................................ ................. 4 5. ball description ................................ ................................ ................................ ...................... 5 6. block diagr am ................................ ................................ ................................ ........................... 6 7. functional descripti on ................................ ................................ ................................ ........ 7 7.1 power up and initialization ................................ ................................ ................................ . 7 7.2 programming mode register set command ................................ ................................ ....... 7 7.3 bank activate command ................................ ................................ ................................ .... 7 7.4 read and write access modes ................................ ................................ .......................... 7 7.5 burst read command ................................ ................................ ................................ ........ 8 7.6 burst command ................................ ................................ ................................ .................. 8 7.7 read interru pted by a read ................................ ................................ ................................ 8 7.8 read interrupted by a write ................................ ................................ ................................ 8 7.9 write interrupted by a write ................................ ................................ ................................ 8 7.10 write interrupted by a read ................................ ................................ ................................ 8 7.11 burst stop command ................................ ................................ ................................ .......... 9 7.12 addressing sequence of sequential mode ................................ ................................ ......... 9 7.13 addressing sequence of interleave mode ................................ ................................ .......... 9 7.14 auto - precharge command ................................ ................................ ................................ 10 7.15 precharge command ................................ ................................ ................................ ........ 10 7.16 self refresh command ................................ ................................ ................................ ..... 10 7.17 power down mode ................................ ................................ ................................ ............ 11 7.18 no operation command ................................ ................................ ................................ ... 11 7.19 d eselect command ................................ ................................ ................................ .......... 11 7.20 clock suspend mode ................................ ................................ ................................ ........ 11 8. operation mode ................................ ................................ ................................ ...................... 12 9. electrical character istics ................................ ................................ ............................. 13 9. 1 absolute maximum ratings ................................ ................................ .............................. 13 9.2 recommended dc operating conditions ................................ ................................ ........ 13
w9864g6jb publication release date: jun. 25 , 2010 - 2 - revision a 0 1 9.3 capacitance ................................ ................................ ................................ ...................... 13 9.4 dc character istics ................................ ................................ ................................ ............ 14 9.5 ac characteristics and operating condition ................................ ................................ .... 15 10. timing waveforms ................................ ................................ ................................ .................. 18 10.1 command input timing ................................ ................................ ................................ ..... 18 10.2 read timing ................................ ................................ ................................ ...................... 19 10.3 control timing of input/output data ................................ ................................ ................. 20 10.4 mode register set cycle ................................ ................................ ................................ .. 21 11. operatinoperating ti ming example ................................ ................................ ............... 22 11.1 interleaved bank read (burst length = 4, cas latency = 3) ................................ .......... 22 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto - precharge) ............... 23 11.3 interleaved ban k read (burst length = 8, cas latency = 3) ................................ .......... 24 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto - precharge) ............... 25 11.5 interleaved bank write (burst length = 8) ................................ ................................ ....... 26 11.6 interleaved bank write (burst length = 8, auto - precharge) ................................ ............ 27 11.7 page mode read (burst length = 4, cas latency = 3) ................................ ................... 28 11.8 page mode read/write (burst length = 8, cas latency = 3) ................................ ......... 29 11.9 auto - precharge read (burst length = 4, cas latency = 3) ................................ ............ 30 11.10 auto - precharge write (burst length = 4) ................................ ................................ .......... 31 11.11 auto refresh cycle ................................ ................................ ................................ ........... 32 11.12 self refresh cycle ................................ ................................ ................................ ............ 33 11.13 bust read and single write (burst length = 4, cas latency = 3) ................................ .. 34 11.14 power down mode ................................ ................................ ................................ ............ 35 11.15 auto - precharge timing (write cycle) ................................ ................................ ............... 36 11.16 auto - precharge timing (read cycle) ................................ ................................ ............... 37 11.17 timing chart of read to write cycle ................................ ................................ ................ 38 11.18 timing chart of write to read cycle ................................ ................................ ................ 38 11.19 timing chart of burst stop cycle (burst stop command) ................................ ............... 39 11.20 timing chart of burst stop cycle (precharge command) ................................ ................ 39 11.21 cke/dqm input timing (write cycle) ................................ ................................ .............. 40 11.22 cke/dqm input timing (read cycle) ................................ ................................ .............. 41 12. package specificatio n ................................ ................................ ................................ ......... 42 12.1 vfbga 60 balls (6.4x10.1 mm 2 , ball pitch:0.65mm, ? =0.4mm) ................................ ...... 42 13. revision history ................................ ................................ ................................ ..................... 43
w9864g6jb publication release date: jun. 25 , 2010 - 3 - revision a 0 1 1. general description w9864g6jb is a high - speed synchronous dynamic random access memory (sdram), organized as 1 m words ? 4 banks ? 16 bits. w9864g6jb delivers a data bandwidth of up to 166 m words per second. for different application, w9864g6jb is sorted into the following speed grades : - 6 / - 6 i / - 6a and - 7 . t he - 6 and - 6i is compliant to the 166m h z/cl3 specification ( the - 6i industrial grade , - 6a automotive grade which is guaranteed to support - 40c ~ 85c ) . the - 7 parts can run up to 143mhz/cl 3 and with t rp = 18ns . accesses to the sdram are burst oriented. consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an active command. column addresses are automatically generated by the sdram internal counter in bu rst operation. random column read is also possible by providing its address at each clock cycle . the multiple bank nature enables interleaving among internal banks to hide the precharging time.by having a programmable mode register, the system can change b urst length, latency cycle, interleave or sequential burst to maximize its performance. w9864g6jb is ideal for main memory in high performance applications . 2. features ? 3.3v ? 0.3v for - 6 / - 6i / - 6a speed grade s power supply ? 2. 7v~3.6v for - 7 speed grade power s upply ? up to 166 mhz clock frequency ? 1 , 048 , 576 words ? 4 banks ? 16 bits organization ? self refresh mode ? cas latency: 2 and 3 ? burst length: 1, 2, 4, 8 and full page ? burst read, single writes mode ? byte data controlled by ldqm, udqm ? auto - precharge and controlled precharge ? 4k refresh cycles/64 ms ? interface: lvttl ? packaged in vfbga 60 balls pitch=0.6 5mm, using lead free materials with rohs complian t
w9864g6jb publication release date: jun. 25 , 2010 - 4 - revision a 0 1 3. order information part number speed self refresh current (max.) operating temperature w9864g6jb - 6 166m hz /cl3 2 ma 0 c ~ 70 c w9864g6jb - 6 i 166m hz /cl3 2 ma - 4 0 c ~ 85 c w9864g6jb - 6 a 166m hz /cl3 2 ma - 4 0 c ~ 85 c w9864g6jb - 7 1 33mhz /cl 3 2 ma 0 c ~ 70 c 4. ball configuration top view 7 6 2 1 c b a p n g d e m h l f k r j vss vss dq14 dq13 dq12 dq10 dq8 nc nc nc cke a11 a8 a6 dq9 dq15 a4 vssq vddq dq11 vssq nc vss udq m clk nc a9 a7 a5 vddq vdd vdd dq1 dq2 dq3 dq5 dq7 nc we# cas# cs# bs0 a10 a1 dq6 dq0 a3 vddq vssq dq4 vddq nc vdd ldqm ras# nc bs1 a0 a2 vssq vss vss dq14 dq13 dq12 dq10 dq8 nc nc nc cke a11 a8 a6 dq9 dq 15 a4 vssq vddq dq11 vssq nc vss udqm clk nc a9 a7 a5 vddq vdd vdd dq1 dq2 dq3 dq5 dq7 nc we# cas# cs# bs0 a10 a1 dq6 dq0 a3 vddq vssq dq4 vddq nc vdd ldqm ras# nc bs1 a0 a2 vssq 7 6 2 1 bottom view
w9864g6jb publication release date: jun. 25 , 2010 - 5 - revision a 0 1 5. ball description ball l ocation ball name function description n6 , p7 , p6 , r6 , r2 , p2 , p1, n 2, n1 , m2 , n7 , m1 a0 ? a11 address multiplexed p ins for row and column address. row address: a0 ? a11. column address: a0 ? a7. a10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by bs0, bs1. m 7 , m 6 bs0, bs1 bank select select bank to activate during row address latch time, or bank to read/write during address latch time. a 6 , b7 , c7 , d 7, d6 , e 7, f7 , g7 , g1 , f1 , e1, d2 , d 1, c1 , b 1, a2 dq0 ? dq15 data input/ output multiplexed pins for data output and input. l7 chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. k6 row address strobe command input. when sampled at the rising edge of the clock , and defin e the operation to be executed. k7 column address strobe referred to j7 write enable referred to j2, j6 udqm , ldqm input/output mask the output buffer is placed at hi - z (with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. k2 clk clock inputs system clock used to sample inputs on the rising edge of clock. l1 cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. a7, h6, r7 v dd power power for input buffers and logic circuit inside dram. a1, h2, r1 v ss ground ground for input buffers and logic circuit inside dram. b6, c2, e6, f2 v ddq power for i/o buffer separated power from v dd , to improve dq noise immunity. b2, c6, e2, f6 v ssq ground for i/o buffer separated ground from v ss , to improve dq noise immunity. g2, g6, h1, h7, j1, k1, l2, l6 nc no connection no connection cs ras cas we
w9864g6jb publication release date: jun. 25 , 2010 - 6 - revision a 0 1 6. block diagram dq0 dq15 udqm ldqm clk cke a10 clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 4096 * 256 * 16 row decoder row decoder row decoder row decoder a0 a9 bs0 bs1 cs ras cas we a11
w9864g6jb publication release date: jun. 25 , 2010 - 7 - revision a 0 1 7. functional description 7.1 power up and initialization the default power up state of the mode register is unspecified. the following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. during power up, all v dd and v ddq pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "nop" state. the power up voltage must not exceed v dd + 0.3v on any of the input pins or v dd supplies. after power up, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power up, it is required that the dqm and cke pins be held high during the initial pause period. once all banks h ave been precharged, the mode register set command must be issued to initialize the mode register. an additional eight auto refresh cycles (cbr) are also required before or after programming the mode register to ensure proper subsequent operation. 7.2 programm ing mode register set command after initial power up, the mode register set command must be issued for proper device operation. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issu ed. the mode register set command is activated by the low signals of , , and at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode register set command once a delay equal to t rsc has elapsed. please refer to the next page for mode register set cycle and operation table. 7.3 bank activate command the bank activate command must be applied before any read or write operation can be executed. the operation is similar to ras activate in edo dram . the delay from when the bank activate command is applied to when the first read or write operation can begin must not be less than the ras to cas delay time (t rcd ). once a bank has been activated it must be precharged before another bank activate command can be issued to the same bank. the minimum time interval between successive bank activate commands to the same bank is determined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved bank activate commands (bank a to b ank b and vice versa) is the bank to bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras (max.). 7.4 read and write access modes after a bank has been activated, a read or write cycle can be followed. this is accompl ished by setting high and low at the clock rising edge after minimum of t rcd delay. pin voltage level defines whether the access cycle is a read operation ( high), o r a write operation ( low). the address inputs determine the starting column address. reading or writing to a different row within an activated bank requires the bank be precharged and a new bank activate command be issued. when more than one bank is activated, interleaved bank read or write operations are possible. by using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages c an be realized. read or write commands can also be issued to the same bank or between active banks on every clock cycle. cs ras cas we
w9864g6jb publication release date: jun. 25 , 2010 - 8 - revision a 0 1 7.5 burst read command the burst read command is initiated by applying logic low level to and while holding and high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the mode register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the mode register set up cyc le. table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. 7.6 burst command the burst write command is initiated by applying logic low level to , and while holding high at the rising edge of the clock. the address inputs determine the starting column address. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is iss ued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. data supplied to the dq pins after burst finishes will be ignored. 7.7 read interrupted by a read a burst read may be interrupted by anoth er read command. when the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. the data from the first read command continues to appear on the outputs until the cas l atency from the inter rupting read command the is satisfied. 7.8 read interrupted by a write to interrupt a burst read with a write command, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid data contention on the dq bus. if a read command will issue data on the first and second clocks cycles of the write operation, dqm is needed to insure the dqs are tri - stated. after that point the write command will have control of the dq bus and dqm masking is no longer needed. 7.9 write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst le ngth is satisfied. 7.10 write interrupted by a read a read command will interrupt a burst write operation on the same clock cycle that the read command is activated. the dqs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. when the read command is activated, any residual data from the burst write cycle will be ignored. cs ras cas we
w9864g6jb publication release date: jun. 25 , 2010 - 9 - revision a 0 1 7.11 burst stop command a burst stop command may be used to terminate the existing burst operation but leave the bank op en for future read or write commands to the same page of the active bank, if the burst length is full page. use of the burst stop command during other burst length operations is illegal. the burst stop command is defined by having an d high with and low at the rising edge of the clock. the data dqs go to a high impedance state after a delay, which is equal to the cas latency in a burst read cycle, interrupted by burst stop. 7.12 addressing sequence of sequential mode a column access is performed by increasing the address from the column address which is input to the device. the disturb address is varied by the burst length as shown in table 2. table 2 address sequence of se quential mode d ata access address burst length data 0 n bl = 2 (disturb address is a0) data 1 n + 1 no address carry from a0 to a1 data 2 n + 2 bl = 4 (disturb addresses are a0 and a1) data 3 n + 3 no address carry from a1 to a2 data 4 n + 4 data 5 n + 5 bl = 8 (disturb addresses are a0, a1 and a2) data 6 n + 6 no address carry from a2 to a3 data 7 n + 7 7.13 addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bit in the sequence shown in table 3. table 3 address sequence of interleave mode d ata access address burst length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 2 data 1 a8 a7 a6 a5 a4 a3 a2 a1 data 2 a8 a7 a6 a5 a4 a3 a2 a0 bl = 4 data 3 a8 a7 a6 a5 a4 a3 a2 data 4 a8 a7 a6 a5 a4 a3 a1 a0 bl = 8 data 5 a8 a7 a6 a5 a4 a3 a1 data 6 a8 a7 a6 a5 a4 a3 a0 data 7 a8 a7 a6 a5 a4 a3 cs ras cas we a0 a1 a2 a2
w9864g6jb publication release date: jun. 25 , 2010 - 10 - revision a 0 1 7.14 auto - precharge command if a10 is set to high when the read or write command is issued, then the auto - precharge function is entered. during auto - precharge, a read command will execute as normal with the exception that the active bank will begin to precharge automatically before a ll burst read cycles have been completed. regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. the number of clocks is determined by cas l aten cy. a read or write command with auto - precharge can not be interrupted before the entire burst operation is completed for the same bank. therefore, use of a read, write, or precharge command is prohibited during a read or write cycle with auto - precharge. once the precharge operation has started, the bank ca nnot be reactivated until the precharge time (t rp ) has been satisfied. issue of auto - precharge command is illegal if the burst is set to full page length. if a10 is high when a write command is issued, the write with auto - precharge function is initiated. the sdram automatically enters the precharge operation two clocks delay from the last burst write cycle. this delay is referred to as write t wr . the bank undergoing auto - precharge cannot be reactivated until t wr and t rp are satisfied. this is referred to a s t dal , data - in to active delay (t dal = t wr + t rp ). when using the auto - precharge command, the interval between the bank activate command and the beginning of the internal precharge operation must satisfy t ras (min). 7.15 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is entered when , and are low and is high at the rising edge of the clock. the p recharge command can be used to precharge each bank separately or all banks simultaneously. three address bits, a10, bs0, and bs1 are used to define which bank(s) is to be precharged when the command is issued. after the precharge command is issued, the pr echarged bank must be reactivated before a new read or write access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). 7.16 self refresh command the self refresh command i s defined by having , , and cke held low with high at the rising edge of the clock. all banks must be idle prior to issuing the self refresh command. once the command is registered, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self refresh operation to save power. the device will exit self refresh operation after cke is returned high. any subsequent commands can be issued after t xsr from the end of self refresh c ommand. if, during normal operation, auto refresh cycles are issued in bursts (as opposed to bein g evenly distributed), a burst of 4,096 auto refresh cycles should be completed just prior to entering and just after exiting the self refresh mode. cs ras cas we
w9864g6jb publication release date: jun. 25 , 2010 - 11 - revision a 0 1 7.17 power down mode the power down mode is initiated by holding cke low. all of the receiver circuits except c ke are gated off to reduce the power. the power down mode does not perform any refresh operations, therefore the device can not remain in power down mode longer than the refresh period (t ref ) of the device. the power down mode is exited by bringing cke high. when cke goes high, a no operation command is required on the next rising clock edge, depending on t ck . the input buffers need to be enabled with cke held high for a period equal to t cks (min.) + t ck (min.). 7.18 no operation command the no operation comm and should be used in cases when the sdram is in a idle or a wait state to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when is low with , , and held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.19 deselect command the deselect command pe rforms the same function as a no operation command. deselect command occurs when is brought high, the , , and signals become don't c are. 7.20 clock suspend mode during normal access mode, cke must be held high enabling the clock. when cke is registered low while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. there is a one clock delay between the registration of cke low and the time at which the sdram operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exi ted by bringing cke high. there is a one clock cycle delay from when cke returns high to whe n clock suspend mode is exited. cs ras cas we
w9864g6jb publication release date: jun. 25 , 2010 - 12 - revision a 0 1 8. operati on mode fully synchronous operations are performed to latch the commands at the positive edges of clk. table 1 shows the tru th ta ble for the operation commands. table 1 truth table (note (1), (2)) c ommand d evice s tate cken - 1 cken dqm bs0, 1 a10 a0 - a9, a 11 bank active idle h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l write with auto - precharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with auto - precharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no - operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x auto - refresh idle h h x x x x l l l h self - refresh entry idle h l x x x x l l l h self refresh exit idle (s.r) l l h h x x x x x x x x h l x h x h x x clock suspend mode entry active h l x x x x x x x x power down mode entry idle active (5) h h l l x x x x x x x x h l x h x h x h clock suspend mode exit active l h x x x x x x x x power down mode exit any ( p ower d own) l l h h x x x x x x x x h l x h x h x h data write/output enable active h x l x x x x x x x data w rite/output disable active h x h x x x x x x x notes: (1) v = valid, x = don't care, l = low level, h = high level (2) cken signal is input leve l when commands are provided. (3) these are state of bank designated by bs0, bs1 signals. (4) device state is full page burst operation. (5) power down mode can not be entered in the burst cycle. when this command asserts in the burst cycle, device state is clock suspend mode. cs ras cas we
w9864g6jb publication release date: jun. 25 , 2010 - 13 - revision a 0 1 9. electrical characteristics 9.1 a bsolute m aximum r atings p arameter s ymbol r ating u nit notes input, output voltage v in , v out - 0. 5 ~ v dd + 0. 5 ( ? 4.6v max.) v 1 power supply voltage v dd , v ddq - 0. 5 ~ 4.6 v 1 operating temperature ( - 6/ - 7) t opr 0 ~ 70 c 1 operating temperature ( - 6i / - 6a ) t opr - 4 0 ~ 85 c 1 storage temperature t stg - 55 ~ 150 c 1 soldering temperature (10s) t solder 260 c 1 power dissipation p d 1 w 1 short circuit output current i out 50 ma 1 note: 1. exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device . 9.2 recommended dc operating conditions (t a = 0 to 70 c for - 6/ - 7 , t a = - 40 to 85 c for - 6 i / - 6a ) p arameter s ym. m in . t yp . m ax . u nit notes power supply voltage for - 6/ - 6i / - 6a v dd 3.0 3.3 3.6 v 2 power supply voltage for - 7 v dd 2.7 - 3.6 v 2 power supply voltage for - 6/ - 6i (for i/o buffer) v ddq 3.0 3.3 3.6 v 2 power supply voltage for - 7 (for i/o buffer) v dd q 2.7 - 3.6 v 2 input high voltage v ih 2.0 - v cc + 0.3 v 2 input low voltage v il - 0.3 - 0.8 v 2 note : v ih (max) = v dd / v dd q +1. 5 v for pulse width < 5 ns v il (min) = v ss / v ss q - 1. 5 v for pulse width < 5 ns 9.3 capacitance (v dd = 3 .3 v 0.3v for - 6 / - 6 i / - 6a , v dd = 2.7v - 3.6v for - 7, t a = 25 c , f = 1 mhz) p arameter s ym. m in . m ax . u nit input capacitance (a0 to a11, bs0, bs1, , , , , cke) c i 1 2.5 4 pf input capacitance (clk) c clk 2.5 4 pf input/output capacitance (dq0 ? dq15) c o 4 6.5 pf input capacitance dqm c i 2 3.0 5. 5 pf note: these parameters are periodically sampled and not 100% tested cs ras cas we
w9864g6jb publication release date: jun. 25 , 2010 - 14 - revision a 0 1 9.4 dc characteristics ( v dd = 3 .3 v 0.3v for - 6, v dd = 2.7v - 3.6v for - 7 on t a = 0 to 70 c , v dd = 3 .3 v 0.3v for - 6i / - 6a on t a = - 40 to 85 c ) p arameter s ym . m ax . u nit n otes - 6 /6i / - 6a - 7 operating current t ck = min., t rc = min. active precharge command cycling without burst operation 1 b ank o peration i dd1 5 0 45 3 standby current t ck = min., = v ih v i h /l = v ih (min.) /v il (max.) bank: inactive state cke = v ih i dd2 2 5 2 0 3 cke = v il (power d own mode) i dd2p 2 2 3 standby current clk = v il , = v ih v ih/l = v ih (min.) /v il (max.) bank: inactive state cke = v ih i dd2s 1 2 1 2 cke = v il (power d own mode) i dd2ps 2 2 ma no operating current t ck = min., = v ih (min.) bank: active state (2 b anks) cke = v ih i dd3 35 30 cke = v il (power down mode) i dd3p 1 2 1 2 burst operating current ( t ck = min.) read/ write command cycling i dd4 7 5 70 3, 4 auto refresh current ( t ck = min.) auto refresh command cycling i dd5 6 0 55 3 self refresh current self refresh mode (cke = 0.2v) i dd6 2 2 p arameter symbol m in . m ax . u nit n otes input leakage current (0v ? v in ? v dd , all other pins not under test = 0v) i i(l) - 5 5 a output leakage current (output disable, 0v ? v out ? v ddq ) l o(l) - 5 5 a lvttl output h level voltage (i out = - 2 ma ) v oh 2.4 - v lvttl output l level voltage (i out = 2 ma ) v ol - 0.4 v cs
w9864g6jb publication release date: jun. 25 , 2010 - 15 - revision a 0 1 9.5 ac characteristics and operating condition (v dd = 3 .3 v 0.3v for - 6 , v dd = 2.7v - 3.6v for - 7 on t a = 0 to 70 c , v dd = 3 .3 v 0.3v for - 6i / - 6a on t a = - 40 to 85 c ) (notes: 5, 6) p arameter s ym . - 6 / - 6i / - 6a - 7 u nit n otes m in . m ax . m in . m ax . ref/active to ref/active command period t rc 60 6 5 ns active to precharge command period t ras 42 100000 45 100000 active to read/write command delay time t rcd 1 5 2 0 read/write(a) to read/write(b)command period t ccd 1 1 t ck precharge to active(b) command period t rp 1 5 18 ns active(a) to active(b) command period t r r d 12 1 4 write recovery time cl* = 2 t wr 2 2 t ck cl* = 3 2 2 clk cycle time cl* = 2 t ck 7.5 1000 10 1000 cl* = 3 6 1000 7 1000 clk high level width t ch 2 2 9 clk low level width t cl 2 2 9 access time from clk cl* = 2 t ac 6 6 10 cl* = 3 5 5.5 10 output data hold time t oh 3 3 10 output data high impedance time t hz 2 6 2 7 7 output data low impedance time t lz 0 0 10 power down mode entry time t sb 0 6 0 7 ns transition time of clk (rise and fall) t t 1 1 data - in - set - up time t ds 1.5 1.5 9 data - in hold time t dh 1 1 9 address set - up time t as 1.5 1.5 9 address hold time t ah 1 1 9 cke set - up time t cks 1.5 1.5 9 cke hold time t ckh 1 1 9 command set - up time t cms 1.5 1.5 9 command hold time t cmh 1 1 9 refresh time t ref 64 64 ms mode register set cycle time t rsc 2 2 t ck e x it self refresh to active command t xsr 72 75 ns *cl = cas latency
w9864g6jb publication release date: jun. 25 , 2010 - 16 - revision a 0 1 notes: 1. operation exceeds absolute maximum ratings may cause permanent damage to the devices. 2. all voltages are referenced to v ss ? 2. 7 v~3.6v power supply for - 7 speed grade. 3. these parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t ck and t rc . 4. these parameters depend on the output loading conditions. specified values are obtained with output open. 5. power up sequence please refer to "functional description" section described before. 6. ac test load diagram. 7. t hz defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 50 ohms 1.4 v ac test load z = 50 ohms output 30pf
w9864g6jb publication release date: jun. 25 , 2010 - 17 - revision a 0 1 8. these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count fractions as whole number) (1) t ch is the pulse width of clk m easured from the positive edge to the negative edge referenced to v ih (min.). t cl is the pulse width of clk measured from the negative edge to the positive edge referenced to v il (max.). (2) a.c latency characteristics cke to clock disable (cke latency) 1 t ck dqm to output to hi - z (read dqm latency) 2 dqm to output to hi - z (write dqm latency) 0 write command to input data (write data latency) 0 to command input ( latency) 0 precharge to dq hi - z lead time cl = 2 2 cl = 3 3 precharge to last valid data out cl = 2 1 cl = 3 2 bust stop command to dq hi - z lead time cl = 2 2 cl = 3 3 bust stop command to last valid data out cl = 2 1 cl = 3 2 read with auto - precharge command to active/ref command cl = 2 bl + t rp t ck + ns cl = 3 bl + t rp write with auto - precharge command to active/ref command cl = 2 ( bl +1) + t rp cl = 3 ( bl +1) + t rp 9 . assumed input rise and fall time (t t ) = 1n s . if tr & tf is longer than 1n s , transient time compensation should be considered, i.e., [(tr + tf)/2 - 1]ns should be added to the parameter 10 . if clock rising time (t t ) is longer than 1n s , (t t /2 - 0.5)n s should be added to the parameter. cs
w9864g6jb publication release date: jun. 25 , 2010 - 18 - revision a 0 1 10. timing waveforms 10.1 command input timing c l k a 0 - a 1 1 b s 0 , 1 v i h v i l t c m h t c m s t c h t c l t t t t t c k s t c k h t c k h t c k s t c k s t c k h c s r a s c a s w e c k e t c m s t c m h t c m s t c m h t c m s t c m h t c m s t c m h t a s t a h t c k
w9864g6jb publication release date: jun. 25 , 2010 - 19 - revision a 0 1 10.2 read timing r e a d c a s l a t e n c y t a c t l z t a c t o h t h z t o h b u r s t l e n g t h r e a d c o m m a n d c l k c s r a s c a s w e a 0 - a 1 1 b s 0 , 1 d q v a l i d d a t a - o u t v a l i d d a t a - o u t
w9864g6jb publication release date: jun. 25 , 2010 - 20 - revision a 0 1 10.3 control timing of input /output data t c m h t c m s t c m h t c m s t d s t d h t d s t d h t d s t d h t d s t d h v a l i d d a t a - o u t v a l i d d a t a - o u t v a l i d d a t a - o u t v a l i d d a t a - i n v a l i d d a t a - i n v a l i d d a t a - i n v a l i d d a t a - i n t c k h t c k s t c k h t c k s t d s t d h t d s t d h t d h t d s t d s t d h v a l i d d a t a - i n v a l i d d a t a - i n v a l i d d a t a - i n v a l i d d a t a - i n t c m h t c m s t c m h t c m s t o h t a c t o h t a c t o h t h z o p e n t l z t a c t o h t a c t c k h t c k s t c k h t c k s t o h t a c t o h t a c t o h t a c t o h t a c v a l i d d a t a - o u t v a l i d d a t a - o u t v a l i d d a t a - o u t c l k d q m d q 0 ~ 1 5 ( w o r d m a s k ) ( c l o c k m a s k ) c l k c k e d q 0 ~ 1 5 c l k c o n t r o l t i m i n g o f i n p u t d a t a c o n t r o l t i m i n g o f o u t p u t d a t a ( o u t p u t e n a b l e ) ( c l o c k m a s k ) d q m d q 0 ~ 1 5 c k e c l k d q 0 ~ 1 5
w9864g6jb publication release date: jun. 25 , 2010 - 21 - revision a 0 1 10.4 mode register set cycle a 0 a 3 a d d r e s s i n g m o d e 0 s e q u e n t i a l 1 i n t e r l e a v e a 0 a 9 s i n g l e w r i t e m o d e 0 b u r s t r e a d a n d b u r s t w r i t e 1 b u r s t r e a d a n d s i n g l e w r i t e a 0 a 2 a 1 a 0 a 0 0 0 0 a 0 0 0 1 a 0 0 1 0 a 0 0 1 1 a 0 1 0 0 a 0 1 0 1 a 0 1 1 0 a 0 1 1 1 b u r s t l e n g t h s e q u e n t i a l i n t e r l e a v e 1 1 2 2 4 4 8 8 r e s e r v e d r e s e r v e d f u l l p a g e c a s l a t e n c y r e s e r v e d r e s e r v e d 2 3 r e s e r v e d a 0 a 6 a 5 a 4 a 0 0 0 0 a 0 0 1 0 a 0 0 1 1 a 0 1 0 0 a 0 0 0 1 * " r e s e r v e d " s h o u l d s t a y " 0 " d u r i n g m r s c y c l e . t r s c t c m s t c m h t c m s t c m h t c m s t c m h t c m s t c m h t a s t a h c l k c s r a s c a s w e a 0 - a 1 1 b s 0 , 1 r e g i s t e r s e t d a t a n e x t c o m m a n d a 0 a 1 a 2 a 3 a 4 a 5 a 6 b u r s t l e n g t h a d d r e s s i n g m o d e c a s l a t e n c y ( t e s t m o d e ) a 8 a 0 a 7 a 9 a 0 w r i t e m o d e a 1 0 b s 0 a 0 a 1 1 " 0 " " 0 " " 0 " " 0 " " 0 " r e s e r v e d b s 1 " 0 " r e s e r v e d
w9864g6jb publication release date: jun. 25 , 2010 - 22 - revision a 0 1 11. operatinoperating ti ming example 11.1 interleaved bank read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k d q c k e d q m a 0 - a 9 , a 1 1 a 1 0 w e c s t r c t r c t r c t r c t r a s t r p t r a s t r p t r p t r a s t r a s t r c d t r c d t r c d t r c d t a c t a c t a c t a c t r r d t r r d t r r d t r r d a c t i v e r e a d a c t i v e r e a d a c t i v e a c t i v e a c t i v e r e a d r e a d p r e c h a r g e p r e c h a r g e p r e c h a r g e r a a r b b r a c r b d r a e r a a c a w r b b c b x r a c c a y r b d c b z r a e a w 0 a w 1 a w 2 a w 3 b x 0 b x 1 b x 2 b x 3 c y 0 c y 1 c y 2 c y 3 r a s c a s b s 1 b s 0 b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w9864g6jb publication release date: jun. 25 , 2010 - 23 - revision a 0 1 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto - precharge) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k c k e d q m a 0 - a 9 , a 1 1 a 1 0 b s 1 w e c a s r a s c s b s 0 t r c t r c t r c t r a s t r p t r a s t r p t r a s t r p t r c d t r c d t r c d t a c t a c t a c t a c t r r d t r r d t r r d t r r d a c t i v e r e a d a c t i v e r e a d a c t i v e a c t i v e a c t i v e r e a d r e a d t r c r a a r a c r b d r a e d q a w 0 a w 1 a w 2 a w 3 b x 0 b x 1 b x 2 b x 3 c y 0 c y 1 c y 2 c y 3 d z 0 * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g a p * a p * r a a c a w r b b c b x r a c c a y r b d r a e c b z r b b a p * t r c d b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w9864g6jb publication release date: jun. 25 , 2010 - 24 - revision a 0 1 11.3 interleaved bank read (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r a s t r p t r p t r a s t r c d t r c d t r c d t r r d t r r d r a a r a a c a x r b b r b b c b y r a c r a c c a z a x 0 a x 1 a x 2 a x 3 a x 4 a x 5 a x 6 b y 0 b y 1 b y 4 b y 5 b y 6 b y 7 c z 0 c l k d q c k e d q m a 0 - a 9 , a 1 1 a 1 0 b s 1 w e c a s r a s c s a c t i v e r e a d p r e c h a r g e a c t i v e r e a d p r e c h a r g e a c t i v e t a c t a c r e a d p r e c h a r g e t a c b s 0 b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w9864g6jb publication release date: jun. 25 , 2010 - 25 - revision a 0 1 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto - precharge) a 0 - a 9 , a 1 1 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r a s t r p t r a s t r c d t r c d t r c d t r r d t r r d a x 0 a x 1 a x 2 a x 3 a x 4 a x 5 a x 6 a x 7 b y 0 b y 1 b y 4 b y 5 b y 6 c z 0 r a a r a a c a x r b b r b b c b y r a c r a c c a z * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g a c t i v e r e a d a c t i v e a c t i v e r e a d t a c t a c t a c c l k d q c k e d q m a 1 0 w e c a s r a s c s r e a d a p * a p * b s 1 b s 0 t r a s t r p b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w9864g6jb publication release date: jun. 25 , 2010 - 26 - revision a 0 1 11.5 interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r a s t r p t r a s t r c d t r c d t r c d t r r d t r r d r a a r a a c a x r b b r b b c b y r a c r a c c a z a x 0 a x 1 b y 4 b y 5 b y 6 b y 7 c z 0 c z 1 c z 2 w r i t e p r e c h a r g e a c t i v e a c t i v e w r i t e p r e c h a r g e a c t i v e w r i t e c l k d q c k e d q m a 0 - a 9 , a 1 1 a 1 0 b s 1 w e c a s r a s c s i d l e b a n k # 0 b a n k # 1 b a n k # 2 b a n k # 3 b s 0 a x 4 a x 5 a x 6 a x 7 b y 0 b y 1 b y 2 b y 3
w9864g6jb publication release date: jun. 25 , 2010 - 27 - revision a 0 1 11.6 interleaved bank write (burst length = 8, auto - precharge) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r c t r a s t r p t r a s t r c d t r c d t r c d t r r d t r r d r a a r a a c a x r b b r b b c b y r a b r a c a x 0 a x 1 a x 4 a x 5 a x 6 a x 7 b y 0 b y 1 b y 2 b y 3 b y 4 b y 5 b y 6 b y 7 c z 0 c z 1 c z 2 c a z * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g c l k d q c k e d q m a 0 - a 9 , a 1 1 a 1 0 b s 1 w e c a s r a s c s a c t i v e w r i t e w r i t e a c t i v e b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 a p * a c t i v e w r i t e a p * b s 0
w9864g6jb publication release date: jun. 25 , 2010 - 28 - revision a 0 1 11.7 page mode read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t c c d t c c d t c c d t r a s t r a s t r c d t r c d t r r d r a a r a a c a i r b b r b b c b x c a y c a m c b z a 0 a 1 a 2 a 3 b x 0 b x 1 a y 0 a y 1 a y 2 a m 0 a m 1 a m 2 b z 0 b z 1 b z 2 b z 3 * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g c l k d q c k e d q m a 0 - a 9 , a 1 1 a 1 0 b s 1 w e c a s r a s c s a c t i v e r e a d a c t i v e r e a d r e a d r e a d r e a d p r e c h a r g e t a c t a c t a c t a c t a c b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 a p * b s 0
w9864g6jb publication release date: jun. 25 , 2010 - 29 - revision a 0 1 11.8 page mode read/write (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 t r a s t r c d t w r r a a r a a c a x c a y a x 0 a x 1 a x 2 a x 3 a x 4 a x 5 a y 1 a y 0 a y 2 a y 4 a y 3 q q q q q q d d d d d c l k d q c k e d q m a 0 - a 9 , a 1 1 a 1 0 b s 1 w e c a s r a s c s a c t i v e r e a d w r i t e p r e c h a r g e t a c b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 b s 0
w9864g6jb publication release date: jun. 25 , 2010 - 30 - revision a 0 1 11.9 auto - precharge read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k d q c k e d q m a 0 - a 9 , a 1 1 a 1 0 w e c a s r a s c s b s 1 t r c t r a s t r p t r a s t r c d t r c d t a c t a c a c t i v e r e a d a p * a c t i v e r e a d a p * r a a r a b r a a c a w r a b c a x a w 0 a w 1 a w 2 a w 3 * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 b s 0 b x 0 b x 2 b x 1 b x 3
w9864g6jb publication release date: jun. 25 , 2010 - 31 - revision a 0 1 11.10 auto - precharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k d q c k e d q m a 0 - a 9 , a 1 1 a 1 0 w e c a s r a s c s b s 1 t r c t r c t r p t r a s t r p r a a t r c d t r c d r a b r a c r a a r a b c a x r a c b x 0 b x 1 b x 2 b x 3 a c t i v e a c t i v e w r i t e a p * a c t i v e w r i t e a p * * a p i s t h e i n t e r n a l p r e c h a r g e s t a r t t i m i n g b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3 t r a s b s 0 c a w a w 0 a w 1 a w 2 a w 3
w9864g6jb publication release date: jun. 25 , 2010 - 32 - revision a 0 1 11.11 auto r efresh cycle 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 a l l b a n k s p r e c h a g e a u t o r e f r e s h a u t o r e f r e s h ( a r b i t r a r y c y c l e ) t r c t r p t r c c l k d q c k e d q m a 0 - a 9 , a 1 1 a 1 0 w e c a s r a s c s b s 0 , 1
w9864g6jb publication release date: jun. 25 , 2010 - 33 - revision a 0 1 11.12 self r efresh cycle c l k d q c k e d q m a 0 - a 9 , a 1 1 a 1 0 b s 0 , 1 w e c a s r a s c s t c k s t s b t c k s a l l b a n k s p r e c h a r g e s e l f r e f r e s h e n t r y a r b i t r a r y c y c l e t r p s e l f r e f r e s h c y c l e t x s r n o o p e r a t i o n / c o m m a n d i n h i b i t s e l f r e f r e s h e x i t
w9864g6jb publication release date: jun. 25 , 2010 - 34 - revision a 0 1 11.13 bust read and single write (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 c l k c s r a s c a s w e b s 1 b s 0 a 1 0 a 0 - a 9 , a 1 1 d q m c k e d q t r c d r b a r b a c b v c b w c b x c b y c b z a v 0 a v 1 a v 2 a v 3 a w 0 a x 0 a y 0 a z 0 a z 1 a z 2 a z 3 q q q q d d d q q q q t a c t a c r e a d r e a d s i n g l e w r i t e a c t i v e b a n k # 0 i d l e b a n k # 1 b a n k # 2 b a n k # 3
w9864g6jb publication release date: jun. 25 , 2010 - 35 - revision a 0 1 11.14 power down mode 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 r a a c a a r a a c a x r a a r a a a x 0 a x 1 a x 2 a x 3 t s b t c k s t c k s t c k s t s b t c k s a c t i v e s t a n d b y p o w e r d o w n m o d e p r e c h a r g e s t a n d b y p o w e r d o w n m o d e a c t i v e n o p p r e c h a r g e n o p a c t i v e n o t e : t h e p o w e r d o w n m o d e i s e n t e r e d b y a s s e r t i n g c k e " l o w " . a l l i n p u t / o u t p u t b u f f e r s ( e x c e p t c k e b u f f e r s ) a r e t u r n e d o f f i n t h e p o w e r d o w n m o d e . w h e n c k e g o e s h i g h , c o m m a n d i n p u t m u s t b e n o o p e r a t i o n a t n e x t c l k r i s i n g e d g e . v i o l a t i n g r e f r e s h r e q u i r e m e n t s d u r i n g p o w e r - d o w n m a y r e s u l t i n a l o s s o f d a t a . c l k d q c k e d q m a 0 - a 9 , a 1 1 a 1 0 b s w e c a s r a s c s r e a d
w9864g6jb publication release date: jun. 25 , 2010 - 36 - revision a 0 1 11.15 auto - precharge timing (write cycle) act 0 1 3 2 (1) cas latency = 2 (a) burst length = 1 dq 4 5 7 6 8 9 11 10 write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 act ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 (2) cas latency = 3 (a) burst length = 1 dq write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 twr twr twr twr twr twr twr twr 12 act represents the write with auto precharge command. represents the start of internal precharing. represents the bank active command. write ap act act when the /auto precharge command is asserted,the period from bank activate command to the start of intermal precgarging must be at least tras (min). note ) clk
w9864g6jb publication release date: jun. 25 , 2010 - 37 - revision a 0 1 11.16 auto - precharge timing (read cycle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note ) t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp
w9864g6jb publication release date: jun. 25 , 2010 - 38 - revision a 0 1 11.17 timing chart of read to write cycle 11.18 timing chart of write to read cycle note: the output data must be masked by dqm to avoid i/o conflict 11 10 9 8 7 6 5 4 3 2 1 0 (1) cas latency= 2 in the case of burst length = 4 read read write write dq dq ( b ) command dqm dqm d0 d1 d2 d3 d0 d1 d2 d3 ( a ) command (2) cas latency= 3 read write read write d0 d1 d2 d3 ( a ) command dq dq dqm ( b ) command dqm d0 d1 d2 d3 read write 0 11 10 9 8 7 6 5 4 3 2 1 q0 read q1 q2 q3 read read write write q0 q1 q2 q3 write q0 q1 q2 q3 d0 d1 dq dq ( a ) command dq dq dqm ( b ) command dqm ( a ) command ( b ) command dqm dqm in the c as e of b urs t length=4 (1) cas latency= 2 (2) cas latency= 3 d0 d0 d1 q0 q1 q2 q3 d0
w9864g6jb publication release date: jun. 25 , 2010 - 39 - revision a 0 1 11.19 timing chart of burst stop cycle (burst stop command) 11.20 timing chart of burst stop cycle (precharge command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq q0 q1 q2 q3 bst ( a ) cas latency =2 c omma nd ( b )cas latency = 3 (1) read cycle q4 (2) write cycle c omma nd read c omma nd q0 q1 q2 q3 q4 q0 q1 q2 q3 q4 dq dq write bst note: represents the burst stop command bst 0 1 11 10 9 8 7 6 5 4 3 2 ( 1 ) read cycle ( a ) cas latency = 2 command q 0 q 1 q 2 q 3 q 4 prcg read ( b ) cas latency = 3 command q 0 q 1 q 2 q 3 q 4 prcg read dq dq ( 2 ) write cycle command q 0 q 1 q 2 q 3 q 4 prcg write dq dqm twr
w9864g6jb publication release date: jun. 25 , 2010 - 40 - revision a 0 1 11.21 cke/dqm input timing (write cycle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk
w9864g6jb publication release date: jun. 25 , 2010 - 41 - revision a 0 1 11.22 cke/dqm input timing (read cycle) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq q5 q4 ( 3 ) q4 clk clk clk
w9864g6jb publication release date: jun. 25 , 2010 - 42 - revision a 0 1 12. package specificatio n 12.1 vfbga 60 ball s (6.4 x 10.1 mm 2 , ball pitch:0.65mm, ? =0.4mm) a a 1 s e a t i n g p l a n e 0 . 4 5 r e f . 0 . 2 1 r e f . b a l l l a n d b a l l o p e n i n g n o t e : b a l l l a n d : 0 . 4 5 m m / b a l l o p e n i n g : 0 . 3 5 m m a 1 d d 2 e 2 e y b e m i n m i n n o m n o m m a x m a x 1 . 1 0 0 . 3 7 1 0 . 0 1 0 . 1 1 0 . 2 0 . 2 7 6 . 3 0 6 . 4 0 6 . 5 0 0 . 3 5 0 . 4 5 0 . 6 5 0 . 4 0 0 . 3 9 3 7 0 . 3 9 7 6 0 . 4 0 1 5 0 . 0 1 0 6 0 . 0 1 4 5 0 . 0 4 3 3 0 . 2 4 8 0 0 . 2 5 1 9 0 . 2 5 5 9 0 . 0 1 4 5 0 . 0 1 5 7 0 . 0 1 8 5 0 . 0 2 5 5 0 . 1 5 3 5 r e f . 0 . 0 0 3 1 r e f . 0 . 3 5 8 2 r e f . 9 . 1 0 r e f . 3 . 9 0 r e f . 0 . 0 8 r e f . s y m b o l d i m e n s i o n i n m m d i m e n s i o n i n i n c h c o n t r o l l i n g d i m e n s i o n : m i l l i m e t e r s a 1 c o r n e r t o p v i e w b o t t o m v i e w a 1 c o r n e r b 1 2 3 4 5 6 7 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r d 2 d e e 2 e e y a
w9864g6jb publication release date: jun. 25 , 2010 - 43 - revision a 0 1 13. revision histor y v ersion d ate p age d escription a 0 1 jun. 25 , 2010 all initial f ormally data shee t important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion con trol instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or seve re property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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